Martin Andraud

Assistant professor

UCLouvain (BE) & Aalto University (FI)

Contact: martin.andraud [at] uclouvain [.] be

Research interests

Processors (accelerators) for edge AI and Tiny ML 100%
ASICs for alternative AI (probabilistic, neurosymbolic) 60%
AI accelerators with emerging non-volatile memories 20%
Test and reliability of AI accelerator SoCs 20%
About me

I am an assistant professor at UCLouvain, Belgium, since January 2024, and a visting professor at Aalto University, Finland. My research interests include ASIC design for alternative AI tasks (e.g., neurosymbolic AI, or probabilistic AI) and online calibration/adaptation methodologies for reliable mixed-signal AI DNN accelerators, in particular based on emerging memory technologies.

I obtained my doctoral degree in TIMA lab, Grenoble-Alpes University, France, in 2016, supervised by Emmanuel Simeu and Haralampos Stratigopoulos. I then worked as a post-doc successively in TU Eindhoven and KU Leuven from 2016 to 2019. Prior to joining UCLouvain in 2024, I was an assistant professor at Aalto University between 2019 and 2023.

I am always interested in collaborating, please do not hesitate to get in touch.

Fresh In

Paper accepted at IEEE CICC 2026

"EinChip", our first silicon-proven accelerator targeting neurosymbolic AI tasks will be presented during CICC 2026, in April (Session 15). This is a collaboration between Aalto University, KU leuven and UCLouvain, taped out on a 16nm Intel process.

Open Positions

Latest publications

You can find me on Google scholar

Latest pre-prints

S. Golipoor, L. Yao, M. Andraud, and S. Sigg “Low-Power On-Device Gesture Recognition with Einsum Networks”, ArXiv pre-print .

S. Zhao, J. Yin and L. Yao, M. Andraud, W. Meert, M. Verhelst, “MC²A: Enabling Algorithm-Hardware Co-Design for Efficient Markov Chain Monte Carlo Acceleration”, ArXiv pre-print .

O. Numan, G. Singh, K. Adam, J. Leslin, A. Korsman, O. Simola, M. Kosunen, J. Ryynänen, M. Andraud “Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration”, ArXiv pre-print .

Peer-reviewed journals

(J11) L. Yao, S. Zhao, M. Trapp, J. Leslin, M. Verhelst, M. Andraud, “LogSumExp: Efficient Approximate Logarithm Acceleration for Embedded Tractable Probabilistic Reasoning”, IEEE Transactions on Circuits and Systems I – Regular papers

(J10) A. M. Mohey, M. Kosunen, J. Ryynänen, M. Andraud, “Low-Power Wide-Range Time-to-Digital Converter for Time-of-Flight Range Finders”, IEEE Access, 2025.

(J9) D.C. Monga, G. Singh, O. Numan, K. Adam, M. Andraud, K.A. Halonen, “TRIM: Thermal auto-compensation for Resistive In-Memory computing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025

Peer-reviewed conferences

(C29) “EinChip: A 4.6/1.5 TOPS/W 6/24b Log-compute Einsum-based Accelerator for Neuro Symbolic AI”, IEEE Custom Integrated Circuit Conference (CICC), 2026, accepted

(C28) O. Numan, G. Singh, K. Adam, M. Andraud, K. Halonen, “Column-Wise IR-Drop Calibration for RRAM-Based CIM: Validation Using a Hierarchical Verilog-A Modeling Framework”, IEEE Electron Devices Technology and Manufacturing Conference, 2026, accepted.

(C25) J. Leslin, M. Trapp, M. Andraud, “Hardware-efficient tractable probabilistic inference for TinyML Neurosymbolic AI applications”, IEEE COINS, 2025.

Other contributions

(O3) L. Yao, M. Trapp, K. Periasamy, J. Leslin, G. Singh, M. Andraud, “Logarithm-Approximate Floating-Point Multiplier for Hardware-efficient Inference in Probabilistic Circuits”, 6th workshop on Tractable Probabilistic Modelling, collocated with the Uncertainty in Artificial Intelligence (UAI) conference, August 2023

Sponsored research

UNION

FNRS / 2026-2029

Goal : Build the next-generation of neurosymbolic AI systems using compute in memory architectures

FAMES Pilot Line

EU - Region Wallone / 2024-2029

My role : Build mixed-signal AI accelerators based on emerging memories and develop online self-calibration to enhance their reliability (https://fames-pilot-line.eu)

(ferrARI) Ferroelectric-enhanced Analog accelerators for Robust, ultra-low power edge Intelligence.

Finnish Research Council / 2024-2027

My role : Develop analog AI accelerators based on ferroelectric components

(SustAIn) Smart Building Sensitive to Daily Sentiment

EU EiC Pathfinder project | 2022-2026

My role : Design embedded intelligence mechanisms for resource-constrained sensor nodes, including probabilistic AI accelerators

(A-core) Aalto RISC-V processor core with embedded AI accelerators

Internal collaboration / 2021-...

Keywords : AI accelerators, In-memory Computing, RISC-V processor

(WHISTLE) When integrated systems gain life experience: towards self-learning circuits with resource-efficient embedded artificial intelligence

Academy of Finland | 2020-2024

Key outputs :Hardware-efficient probabilistic circuits, AutoPC framework

(DIFFER) Digital-intensive IC sensor interface for frequency-modulated gyroscopes

Industry collaboration / 2021-2023

Key outputs : Event-based TDC architectures, time-based accelerator for deep neural networks

(PiCo) Processing in contact, High Density, Ultra Low Power Computing Element

Industry collaboration / 2020-2022

Key output : Acore-CIM: self-calibrated AI acceleration SoC with mixed-signal CIM core

Blog

Papers we write

Monga et al., ISCAS'23

A temperature and process compensation circuit for resistive-based in-memory computing arrays" By Dipesh Monga et al., ISCAS'23

Martin A.
10.07.2023
Papers I Read

TeAAL

"TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators", by Nandeeka Nayak et al.

Martin A.
10.07.2023

Team

Current post-doctoral researchers

Gaurav Singh (UCL) “Reliable mixed-signal Compute-in-Memory Accelerators with emerging memory technologies (FAMES) ” - Starting date: December 2024

Current PhD researchers:

Artuur Astaes (UCL) (Supervisor), “AI accelerators for Neurosymbolic AI”. Starting date: Apr. 2025

Lingyun Yao (AAL) (Supervisor). “Hardware-accelerated Probabilistic circuits for probabilistic edge AI”. Starting date: October 2022

Previous PhD researchers:

Ahmed Mohey (AAL) (Supervisor), “Integrated Circuit (IC) Architectures for Novel Time-Based Sensor Interfaces”. Sept 2021 - Sept. 2025 (Defence on March 27th, 2026).

Karthekeyan Periasamy (AAL) (Supervisor), “Custom hardware accelerators for on-chip probabilistic machine learning”. Apr. 2021 - Feb. 2025 (Defense Pending). Current position: SoC designer, Nokia Finland

Jelin Leslin (AAL) (Supervisor), “Probabilistic Machine Learning Hardware Architectures towards Self Learning Edge AI”. May 2021 - Aug. 2025 (Defense Pending).

Kazybek Adam (AAL) (Supervisor), “In Memory Computing architecture for fully-analog on-chip machine learning accelerators”. Starting date: Oct. 2020 - Oct 2025 (Defense Pending).

Omar Numan (AAL) (Advisor, supervisor Prof. Kari Halonen), “Design of analog and analog-mixed-signal integrated-circuits for analog in-memory computing for AI applications”. Nov 2020 - Oct 2025(Defense Pending). Current position: Researcher at VTT Finland.

Current master thesis students