Martin Andraud

Assistant professor

UCLouvain (BE) & Aalto University (FI)

Contact: martin.andraud [at] uclouvain [.] be

Research interests

Processors (accelerators) for edge AI and Tiny ML 85%
ASICs for alternative AI (probabilistic, neurosymbolic) 95%
Test and reliability of AI accelerator SoCs 70%
AI accelerators with emerging non-volatile memories 70%
About me

I am an assistant professor at UCLouvain, Belgium, since January 2024, and a visting professor at Aalto University, Finland. My research interests include ASIC design for alternative AI tasks (e.g., neurosymbolic AI, or probabilistic AI) and online calibration/adaptation methodologies for reliable mixed-signal AI DNN accelerators, in particular based on emerging memory technologies.

I obtained my doctoral degree in TIMA lab, Grenoble-Alpes University, France, in 2016, supervised by Emmanuel Simeu and Haralampos Stratigopoulos. I then worked as a post-doc successively in TU Eindhoven and KU Leuven from 2016 to 2019. Prior to joining UCLouvain in 2024, I was an assistant professor at Aalto University between 2019 and 2023.

I am always interested in collaborating, please do not hesitate to get in touch.

Fresh In

Paper accepted at IEEE COINS 2025

Our paper "Hardware-efficient tractable probabilistic inference for TinyML Neurosymbolic AI applications" has been accepted at IEEE COINS.

Paper accepted at IEEE TCAD

Our paper "TRIM: Thermal auto-compensation for Resistive In-Memory computing" has been accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems .

Open Positions

Latest publications

You can find me on Google scholar

Peer-reviewed journals

(J8) Ahmed M. Mohey, Jelin Leslin, Gaurav Singh, Marko Kosunen, Jussi Ryynänen, Martin Andraud, “A 22nm All-Digital Time-Domain Neural Network Accelerator for Precision In-Sensor Processing”, IEEE Transactions on VLSI, 2024.

Peer-reviewed conferences

(C23) J. Leslin, M. Trapp, M. Andraud, “Mixed precision HW acceleration in PCs”, the IoT, Edge, and Mobile for Embedded Machine Learning workshop, co-located with The European Conference in Machine Learning, 2024.

(C22) K. Periasamy, J. Leslin, A. Korsman, L. Yao and M. Andraud, "AutoPC: An Open-Source Framework for Efficient Probabilistic Reasoning on FPGA Hardware," 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), 2024.

(C21) L. Yao, M. Trapp, J. Leslin, G. Singh, P. Zhang, K. Periasamy, M. Andraud, “On Hardware-efficient Inference in Probabilistic Circuits”, the 40th Conference on Uncertainty in Artificial Intelligence, 2024.

(C20) G. Singh, O. Numan, D. Monga, M. Andraud and K. Halonen, "On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing," 2024 IEEE European Test Symposium (ETS), The Hague, Netherlands, 2024.

Other contributions

(O3) L. Yao, M. Trapp, K. Periasamy, J. Leslin, G. Singh, M. Andraud, “Logarithm-Approximate Floating-Point Multiplier for Hardware-efficient Inference in Probabilistic Circuits”, 6th workshop on Tractable Probabilistic Modelling, collocated with the Uncertainty in Artificial Intelligence (UAI) conference, August 2023

Sponsored research

FAMES Pilot Line

EU - Region Wallone / 2024-2029

My role : Build mixed-signal AI accelerators based on emerging memories and develop online self-calibration to enhance their reliability

(ferrARI) Ferroelectric-enhanced Analog accelerators for Robust, ultra-low power edge Intelligence.

Finnish Research Council / 2024-2027

My role : Develop analog AI accelerators based on ferroelectric components

(SustAIn) Smart Building Sensitive to Daily Sentiment

EU EiC Pathfinder project | 2022-2026

My role : Design embedded intelligence mechanisms for resource-constrained sensor nodes, including probabilistic AI accelerators

https://fames-pilot-line.eu/

(A-core) Aalto RISC-V processor core with embedded AI accelerators

Internal collaboration / 2021-...

Keywords : AI accelerators, In-memory Computing, RISC-V processor

(WHISTLE) When integrated systems gain life experience: towards self-learning circuits with resource-efficient embedded artificial intelligence

Academy of Finland | 2020-2024

Key outputs :Hardware-efficient probabilistic circuits, AutoPC framework

(DIFFER) Digital-intensive IC sensor interface for frequency-modulated gyroscopes

Industry collaboration / 2021-2023

Key outputs : Event-based TDC architectures, time-based accelerator for deep neural networks

(PiCo) Processing in contact, High Density, Ultra Low Power Computing Element

Industry collaboration / 2020-2022

Key output : Acore-CIM: self-calibrated AI acceleration SoC with mixed-signal CIM core

Blog

Papers we write

Monga et al., ISCAS'23

A temperature and process compensation circuit for resistive-based in-memory computing arrays" By Dipesh Monga et al., ISCAS'23

Martin A.
10.07.2023
Papers I Read

TeAAL

"TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators", by Nandeeka Nayak et al.

Martin A.
10.07.2023

Team

Current post-doctoral researchers

Gaurav Singh (UCL) “Reliable mixed-signal Compute-in-Memory Accelerators with emerging memory technologies (FAMES) ” - Starting date: December 2024

Current PhD researchers

Artuur Astaes (UCL) (Supervisor), “AI accelerators for Neurosymbolic AI”. Starting date: Apr. 2025

Lingyun Yao (AAL) (Supervisor). “Hardware-accelerated Probabilistic circuits for probabilistic edge AI”. Starting date: October 2022

Kazybek Adam (AAL) (Supervisor), “In Memory Computing architecture for fully-analog on-chip machine learning accelerators”. Starting date: Oct. 2020

Ahmed Mohey (AAL) (Supervisor), “Integrated Circuit (IC) Architectures for Novel Time-Based Sensor Interfaces”. Starting date: September 2021

Omar Numan (AAL) (Advisor, supervisor Prof. Kari Halonen), “Design of analog and analog-mixed-signal integrated-circuits for analog in-memory computing for AI applications”. Starting date: November 2020

Previous PhD researchers

Karthekeyan Periasamy (AAL) (Supervisor), “Custom hardware accelerators for on-chip probabilistic machine learning”. Apr. 2021 - Feb. 2025 (Defense Pending). Current position: SoC designer, Nokia Finland

Jelin Leslin (AAL) (Supervisor), “Probabilistic Machine Learning Hardware Architectures towards Self Learning Edge AI”. May 2021 - Aug. 2025 (Defense Pending). Current position:

Current master thesis students